In general, conventional techniques for assembling flip-chip package structures typically utilize lithographically defined mechanical stops in conjunction with a solder reflow process to align components in one or two dimensions. However, such alignment and packaging techniques can be ineffective to accurately align package components due to various tolerances that exist in certain fabrication and assembly processes. For example, when dicing a wafer into a plurality of similar chips, there can be variations in the size of the diced chips (dies) in a range of +/−15 μm. Moreover, when using high speed pick and place tools for flip-chip assembling, there can be variations in the initial chip (die) placement in a range of +/−10 μm. Such variations in chip sizes and placement can result in misalignment of assembled components when using mechanical stops and solder reflow techniques for alignment.